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PE42750
Product Specification
Evaluation Kit Information
The SPDT Switch Evaluation Kit facilitates
customer evaluation of the PE42750 SPDT switch.
The RF common port is connected through a 75 ?
transmission line to J2. Ports 1 and 2 are
connected through 75 ? transmission lines to J1
and J3. A through line connects F connectors J4
and J5. This transmission line can be used to
estimate the PCB loss over the environmental
conditions. J6 provides DC and digital inputs to the
device.
The board is composed of a two metal layer FR4
material with a total thickness of 0.032”. The
transmission lines are hybrid microstrip/coplanar
waveguide with ground plane (28 mil core, 12 mil
width, 12 mil gap).
The provided jumpers short the control pins to
ground for logic low. With the jumper removed the
control input rises to V DD for logic high through the
1 M ? pull up resistor. These resistors will draw
several microamps from V DD. They are not required
for normal operation.
Figure 20. Evaluation Board Layouts
Peregrine Specification 101/0491
Figure 19. Evaluation Board Schematic
Peregrine Specification 102/0586
NOTES:
1. USE 101-0491-01
2. CAUTION:
1
3
5
7
9
11
13
J6
HEADER 14
C1
C2
GND
GND
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
4
6
8
10
12
14
CONTAINS PARTS AND ASSEMBLIES SUSCEPTIBLE
TO DAMAGE BY ELECTROSTATIC DISCHARGE (ESD)
3. ALL TRANSMISION LINES ARE:
C1
DNI
R1
1M
R2
1M
12MIL WIDTH, 12MIL GAPS, 28MIL CORE DIELECTRIC
4.3 Er AND 2.1MIL Cu THICKNESS.
C2
DNI
C3
DNI
J1
CBJE130-2
1
RF1
75 OHM T-Line
1
2
GND
RF1
U1
QFN_12L_3X3
GND
RF2
9
8
75 OHM T-Line
RF2
J3
CBJE130-2
1
J2
CBJE130-2
75 OHM T-Line
3
GND
GND
7
1
RFC
J4
CBJE130-2
75 OHM T-Line
J5
CBJE130-2
1
1
Document No. 70-0334-07 │ www.psemi.com
?2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 10
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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